Here's Apple's background and summary of the invention: "Shift instructions for microprocessor general-purpose registers often take two parameters as operand. The first operand specifies a designation register whose value is being shifted. The second operand is the count operand that specifies the amount by which the register is being shifted. The count operand may be a variable or a constant. If it is a variable, it may be specified as the value contained in another register or in a memory location. If it is a constant, it is defined by a predetermined value at coding time.

Some shift operands in a microprocessor instruction set may be limited to accepting a constant value as the count operand. Some shift instructions are further limited to shifting the register value by a large amount, e.g., shifting by bytes instead of by bits.

Previously, to simulate a shift by a variable amount, programmers have utilized instruction loops. For instance, a loop specifying a value of 1 for the shift count can be called repeatedly a variable amount of times to shift a register value by the desired amount.

"In order to shift in bits instead of bytes, the programmers have previously looked at the microprocessor instruction set to find other shift instructions that allow shifting in bits and have utilized those instructions to simulate the desired shift operation in bits. For example, in the Intel x86 architecture, the instruction for shifting a double quadword (where a word is 16 bits or 2 bytes) does not allow shifting in bits but the instruction for shifting a quadword does allow shifting in bits. Accordingly, in this architecture, some programmers who want to shift a double quadword register would write code to use the quadword shift instruction to generate missing bits from the other side and then would perform a logical `or` operation on them to make the final result.

"Some embodiments present a method of performing a variable shift operation. This method can be used by a microprocessor that does not allow variable shift operation for certain operand sizes. The method simulates a shift instruction that shifts an operand by a shift count. The method identifies a first shift command and a second shift command. The method computes a mask value. The mask value depends on whether the shift count is less than half of the operand size or greater than or equal to half of the operand size. The method uses the mask value to cause one of the first shift command and the second shift command to produce no shift. In some embodiments, the method allows for the shift count to be specified in bytes or in bits.

Many applications require repeated moving of blocks of data from one memory location to other memory locations. Some embodiments provide a method of moving blocks of memory to or from addresses that are not aligned at any specific address location. Each move operation may require one or more shift operations with variable shift count. The move operations may also require bitwise shifting, i.e., shifting the operand a variable number of bit positions.

Some embodiments of the invention simulate a shift operation that cannot perform a variable or bitwise shift, by utilizing smaller shift operations that allow variable or bitwise shift operations. In the examples below, the shift operation that cannot perform variable or bitwise shifting is a double quadword target operation in the Intel.RTM. SSE2 instruction set. However, one of ordinary skill will realize that the invention is applicable to other shift operations that cannot perform variable or bitwise shifting.

In order to simulate a shift operation, a novel algorithm is presented that allows the shift count to be a variable as well as a constant and the shift count can be specified in bytes or bits. The algorithm does not require a branch operation to distinguish between a shift for less than half the length of the operand and a shift equal or grater than half the length of the operand. In the following examples, a `shift double quadword` left operation PSLLDQ of the instruction set of Intel.RTM. SSE2 is used to illustrate how the invention performs variable or bitwise shifting on a double quadword basis. One of ordinary skill will realize that the same method may be applied for shift right operation and for shifting in bits instead of bytes. The same method can also be applied to any other microprocessor instruction set that has the same limitations for a shift operation that only accepts a constant shift count or only shifts in bytes when other smaller shift operations without the limitations are available."

The inventors are Hyeonkuk Jeong and Paul Chang.

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